UVM phases are virtual methods defined within the `uvm_component` class. This class can be extended to create custom components such as scoreboards, monitors, and drivers. When extending this class, only the necessary phases are implemented, it is not mandatory to implement all of them.

Purpose

The primary purpose of UVM phases is to provide a mechanism for synchronization. All components in the testbench execute the same phase in parallel, and they cannot advance to the next phase until all other components have completed the current phase. However, the phases are executed sequentially. For example, the build phase must end in all components before executing the connect phase.

Basic hierarchy

UVM phases can be categorized into three main groups:

1. Build phases: Used to configure and construct the testbench.
   1. build: This phase is responsible for the hierarchical generation of all components. It executes in a top-down manner, initially building the environment, followed by the tests, the scoreboard, and the agents (where the agent’s active or passive configuration is defined).
   2. connect: This phase establishes TLM (Transaction-Level Modeling) connections and handles between all previously generated components. It executes in a bottom-up fashion.
   3. end_of_elaboration: This phase displays the UVM topology and executes other functions required after connections have been established.
   
2. Runtime phases: Where the test is executed and time is consumed.
   1. start_of_simulation: Performs initial runtime configuration.
   2. the next phase runs as 2 parallel threads, and where the time is consumed.

Table 1: Complete list of runtimephases

1. Clean-up phases: Collect and report the results
   1. extract: Data from the scoreboard and coverage is analyzed in this phase.
   2. check: Verifies for mismatches between predicted data and data from the DUT (Device Under Test).
   3. report: Display results or write them info files
   4. final: Complete any remaining actions

Figure 1: UVM_phases diagram. In greyscale the build phase, in red and blue the runtime phase and in greenscale the clean-up phase

Depending on the reference material, the `start_of_simulation` phase may be considered part of either the build phase or the runtime phase. The other build phases, as they do not consume time, are implemented as functions. This is also true for the clean-up phases. The first group of phases is involved in generating and connecting the entire environment, while the last group is used to conclude the simulation, generating reports, performing statistical calculations, closing open files, and so forth.

All phases in the runtime phase, as they consume time, are implemented as tasks. Additionally, each of these phases has a pre-x phase and a post-x phase.

Table 1: Complete list of runtimephases

By adding the “+UVM_ADD_TRACE” argument to the test, you can observe the execution order of the phases in your test. The following is an example capture:

Figure 2: output when the plusarg +UVM_ADD_TRACE is set

Conclusion

The UVM phases are inherent to every UVM test. It is up to the verification engineer’s discretion how to implement them, ensuring optimal test results and efficient use of computing resources.

Bibliography

• https://verificationacademy.com/cookbook/uvm-universal-verification-methodology/
• Salemi, Ray, The UVM Primer: An Introduction to the Universal Verification Methodology, Boston Light Press, (2013)
• https://www.chipverify.com/uvm/uvm-phases

Written by Roberto Millon Tello, Patricio Gallo & Marcelo Pouso
Edited by Adrian Evaraldo
For further inquiries, contact us: info@emtech.com.ar